Monday, February 26, 2007

PCI, Torenza , CELL, Network Processor and Fusion

This won't be a lengthy article as I don't usually spend long time writing a blog :)

Torenza is a good technology, but it is not a totally new technology. Every functions that it tries to provide, exist today. Co-processing existed on all sort of interfaces, with PCI being the most common one. Those co-processing, don't require low latency access by/to the CPU, bandwidth is one single biggest factor. Torenza adds low latency into the picture, which indeed will create a new frontier of co-processing for application requiring low latency at system level wise. However, while it claims to be open, it is not as 'open' as PCI and alls its derivatives. PCI specs are easily available with full details of information, and it is guarantee to be free on the entire technology. Geneseo will fill in the gap for low latency co-processor interfacing and will see a much wider technology adoption, even by being late into the game play. Todays' economy is economy of scales. Whose technology is most open, most used, most industries back up, will win.

While all these are trying to provide more co-processing power at system level, internal dynamic co-processing chip designs already existed or soon to be exist. Perhaps CELL is the most known example of this, where the coprocessing requirement, can be dynamically programmed. I have a strong feeling that the concept were from its own network processor, which IBM exited the business few months before the CELL launched. Intel still sells its IXP range of network processors.

Fusion, to me is just a funky name used for marketing purpose. It is another level down, no dynamic co-processing at runtime, but at design/manufacturing time. It provides jigsaw puzzle ability to AMD to pick and match component within a silicon. Anyway, this technology is not new at all, a single silicon today can actually be packaged into multiple chips SKU, by fusing (or derivative design) some of its components within the silicon. All AMD plans to do on this is to add GPU (and of course some changes to make it homogeneous system wise). AMD is smart enough to target the mobile platform first, which the power is its key strength.

After the internal dynamic co-processing, may be the next step is FPGA within a chip, which will provide even dynamic co-processing nature.

Thursday, February 22, 2007

Barcelona's code name is not K10

So many people were trying to guess the correct code name for the AMD's coming Barcelona processor. INQ (and later those fanbois Sharikou, Scientia and alikes) wished to call it K10. Well, it is not K10.

Guess what, K10 is still under development, so it can't be K10. K9 is just a bad name.

Again, Barcelona's code name 'is not' K10, period.

p/s: K8L is more likely referring to Barcelona