Saturday, July 22, 2006

IMC Myth

There seems to be an overhype on the IMC within the x86 CPU. I am not bashing on the goodness of having IMC and thus lower the memory latency, but my point is that it is simply overhype. Every single piece of feature within a CPU, is an engineering decision in one way and another. The main focus are the overall system performance and the target platform usage models.

Intel's new Core 2 Duo, is wothout the IMC, and yet still out perform the AMD's K8 with IMC, speaks for itself. It is not that Intel will not use IMC, it is just that it does not need it yet.

Then there are people argue about the scalability (about the NUMA vs UMA), saying that the C2d would not scale as good as AMD's; and in 2 years time , AMD's CPU might take the lead again due to this. Well, i wouldn't disagee on this scalability issue and the future possiblity of AMD taking the lead again. But who cares? As a desktop and laptop user, If I were to buy a decent system nowaday, I'd defintely go for Intel's C2D, at least for now. The scalability issue is not my issue, but the Intel's architect and design engineer issue. Some might want to further question this: "yes, intel can raise the FSB frequency and enhance cache design for 2 core or possible 4 cores, but it surely hit bottleneck when it designs 8 core and above". Well, it is not a user's concern. It is again their design team's concern on how to over come this, be it using IMC or other method.

Wait a minute, what about MP? As far as my desktop and laptop concern, I will not be using one , and again, at least in this few years time. Why should I incur such rediculous hardware cost and possibbly the softwatre cost while a decent single multicore processor can do the job?

Having said all that, AMD with its IMC and ccHT (hence NUMA) did give it an advantage at the 4P and above server end. The IMC is definitely not a case at the desktop and laptop end as of now, and not a case in 2P server as well because the dual FSB chipset is available.


Anonymous said...

with imc intel would have to do a whole new processor and not a pentium 3 with steroids. It's too risky for them now. So they put Big l2-cache to lower the fsb effect.

pointer said...

with imc intel would have to do a whole new processor and not a pentium 3 with steroids. It's too risky for them now. So they put Big l2-cache to lower the fsb effect.

well, there are something more than a new processor. The whole platform would have to change as the CPU would gain advantage of the IMC, but the Integrated GPU at the MCH lose the advantage ...

there are actually at least 4 factors the reduce the fsb bottle neck
1) bigger cache (as what you said)
2) shared cache for multithread between 2 core
3) dynamic cache size resulted much bigger cache for single threaded appls
4) higher fsb frequency

and another one, which i'm not sure how smart it is: the prefetcher

enumae said...

"It's too risky for them now."

Thats funny... I think what you meant to say was they don't need it yet, maybe for servers, but not for desktop or mobile. C2D is doing just fine without it.

They have it in the works, CSI and an IMC, release dates are unknown, but from an article I read, mid 2007 will show the first server based chip with it(supposedly).

Anonymous said...

well yeah that was a bit funny, and you are right that maybe only servers need it. I think with imc intel has to reduce cache sizes and the performance will be like amd's. Is CSI enough? HT 3.0 is very nice. BUT if CSI is too much bottleneck again, and maybe they can add cache more again to minimize the latency :D. CSI gives a lot more bandwith and the performance will be great no doubt. ( i'm just specalutating and i'm not a pro in thease things ) Just my thoughts. :)

Anonymous said...

And maybe it's risky too. They needed very good processor in a very fast time. If they would have done imc now with no expirience it would have taken too much time. Conroe is a very good solution for now. It won a lot of their problems in no time.

pointer said...

If they would have done imc now with no expirience it would have taken too much time.

Did you notice that I purposely stated "IMC within x86 CPU"? AMD is certainly not the first one that came out with CPU with IMC and Intel did has a lot of product with the IMC. For example, you can check their range of product on IXP, such as IXP2400 for example.

the sharkie stopper said...

Well, the first results are in.

Even running 64 bit, Conroe frags AMD FX-62.

"The average performance improvement we have seen from Athlon 64 FX-62 equaled 16%, while Core 2 Extreme X6800 demonstrated only 10% average performance boost. This way, there is a certain difference: AMD K8 turns out 6% mode efficient in 64-bit mode than Intel Core. However, this difference cannot compensate for the 20% performance advantage of the Intel Core 2 Duo over the Athlon 64 X2 working at the same clock speed, which we have pointed out in our previous articles. Therefore, we will not change our conclusions about the performance of the new Intel processors even keeping in mind the upcoming launch of 64-bit Windows Vista OS family."

Anonymous said...

pentium 3 with steroids

What kind of comment is that? If a Pentium 3 beats the cr@p out of K8, I would say that speaks volums about the abilities of K8.

Having said that, Conroe is much more than P3. P3 had a 9-stage pipeline, Conroe has 14. P3 was single-issue, Conroe is 4-issue. P3 did not have micro and macro fusion, Conroe does. P3 did not have memory disambiguation, Conroe does. Thus, Conroe looks nothing like P3. It's only when you look at the transition P3->Pentium M->Core 2 the similartities become apperant.

K8 is a good architecture. It's just so that Conroe is better.

Anonymous said...

Is CSI enough? HT 3.0 is very nice.

HT is nothing but a point-to-point interconnect: just like PCI-E (PCI-E is serial, while HT is parallel). Considering that Intel was the one to reach the market with PCI-E, and that most of the definitions in PCI SIG come from Intel, I would argue that Intel has a lot more experience in point-to-point interconnects. From what I hear, CSI could be over-engineered, just because Intel has too many experts in this area.

As for IMC, AMD is not the first company to have IMC, even in x86. It is once again Intel. Intel had an IMC in Timnah. However, with Timnah, Intel placed bets on Rambus memory, and finally the product could not be shipped because Rambus never got mainstream. However, Timnah was working just fine.

In fact, the wrong bet that Intel placed with Timnah (and Rambus) is what has kept Intel away from IMC so far. They do not want to make the same mistake again.

Finally, do not expect an IMC or CSI in mid 07. Intel has said that they will revise their microarchitecture every two years. Considering Conroe came in Q3 06, the best-case bet for next micro-architecture is Q3 08. That is when we will see IMC and CSI (if at all).

Scientia from AMDZone said...

Actually, the comparison between PCI-E and HT is not correct. While both are point to point systems they are not physically the same. PCI-E uses a switching hub to make connections very similar to gigabit ethernet. HT connects directly which is why the latency for HT is lower.

The hub approach works better for larger numbers of connections which is why it is used for I/O cards. However, it is worse for high speed connections. This is why Intel altered the specifications with Geneseo which also improves CSI. Even with this though CSI is still not as good as HT 3.0 which has both distance modes and power saving modes. I don't expect CSI on X86 until 2009 although it might be released on Itanium at the very end of 2008. More likely seems to be that Intel will use a native quad Yorkfield design in 2008.

Solange said...

Thank you for all for very a informative debate, but please, being a knowledgeable Geek Emeritus does not excuse you from butchering the English language.
Use your computer spell check function, it works very fast too. :-)

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